A one-and-a-half-supplier market.
By Memorial Day 2026 the leading-edge foundry race has settled into a shape the industry has not seen since the 28nm era: one dominant supplier with pricing power, one credible alternative for work that isn't bleeding-edge, and one IDM-turned-foundry burning cash to stay in the room. TSMC began N2 volume production in Q4 2025 and is guiding to 100,000 wafers a month by year-end and 200,000 by 2027. Demand has already overrun the original 40,000 plan.
Samsung's second-generation SF2P cleared the ~70% mass-production yield bar in January 2026, the first time in three nodes it has done so before a comparable TSMC process matured. Tesla's $16.5B AI chip deal anchors its order book. Intel's 18A is making Panther Lake tiles in Arizona, but at 20-25% good-die yield, which the company itself calls inadequate for target margins. The strategic question is no longer who has 2nm. It's who can afford to use it.
TSMC Fab 6, Tainan. N2 volume runs from Fab 22 (Kaohsiung) with Fab 20 (Hsinchu) ramping behind it. Photo: 4300streetcar / Wikimedia Commons (CC BY 4.0)
TSMC (Taiwan) the dominant leading-edge foundry; N2 in volume production since Q4 2025.
Samsung Foundry (South Korea) the second source, at ~70% SF2P yield since January 2026.
Intel Foundry (US) running 18A in Arizona, but below the yield its own margins need.
ASML (Netherlands) the sole supplier of the EUV and High-NA scanners all three depend on.
Fabless designers (Apple, NVIDIA, Qualcomm, AMD, Tesla) bid for wafer allocation 12-18 months ahead.
1. A fabless designer tapes out a 2nm-class SoC and books wafer allocation well ahead of production.
2. The foundry fabricates the wafers; yield, the share of good dies, sets the real cost per chip.
3. Advanced packaging then stitches the die to its memory; that step is often the tighter constraint.
4. Wafer price multiplied by yield loss determines the bill-of-materials hit on the finished chip.
5. Finished parts ship to the device maker, months after the allocation was first locked.
Neutral process view. Where a step is single-sourced (TSMC scale, ASML tools) is noted without judgment.
TSMC's pricing restraint is the tell.
The era of node leadership equals market leadership is fracturing. TSMC's N2 wafer runs about $30,000, only a 10-20% premium over N3's $25-27K, well below the 50% hike the rumor mill floated last summer. For a company with monopoly pricing power, that restraint is itself a signal: TSMC needs N2 to fill faster than N3 did, because the real economics now sit one generation out, in N2P and A16 in 2027. High customer concentration in AI and HPC is enough that TSMC is self-limiting its take rate to keep those anchor customers committed.
That leaves the customer exposed in a specific way. A roadmap locked to a single foundry for flagship silicon in 2027-2028 faces a step-function price reset when pricing power migrates to the next node. Samsung at 70% SF2P yield is, for the first time since the Snapdragon 8 Gen 1 stumble, a defensible second source for work that can tolerate a half-node performance gap in exchange for 15-20% wafer-cost relief. Intel's 18A is the opposite case: a genuine technology achievement and, at sub-50% yield through most of 2026, a financial problem its foundry segment can't yet outrun.
A finished wafer. At ~$30K for N2 versus $25-27K for N3, every percentage point of yield is real money. Photo: Inductiveload / Wikimedia Commons (Public domain)
TSMC (sets the pace and the price), Samsung (a credible second source for the first time in a decade, with Tesla, DeepX and Canaan confirmed), ASML (High-NA EXE:5200B tools now in production at Intel and Samsung), and the photoresist makers (JSR, TOK, Shin-Etsu) as TSMC's multi-patterning path to A14 leans harder on chemistry.
Intel Foundry, where 18A is a technology win and a cash-flow problem at once. Any fabless buyer single-sourced on one foundry for 2027-2028 flagship parts. And the comfortable assumption that leading-edge pricing only ever goes down.
The startup opening. The opening is in foundry intelligence and qualification speed: allocation-tracking tools that map capacity rather than contracts, services that compress the 9-12 month Samsung qual cycle, and multi-patterning cost optimization for the A14 era TSMC is steering toward instead of High-NA. The dual-source world creates work that the single-source world never needed.
1. Tom's Hardware: TSMC N2 ramp and Intel 18A yield trajectory (Nov 2025) [6 min]
2. TrendForce: Samsung SF2P yield threshold cleared (Jan 2026) [5 min]
3. TechNode: N2 wafer ASP triangulation (Oct 2025) [4 min]
4. DataCenterDynamics: TSMC 2026 capex guidance (Apr 2026) [5 min]
N2 / 2nm: TSMC's leading-edge process generation; the smallest, fastest, most power-efficient transistors in volume production today.
Yield: the share of chips on a wafer that come out good. Low yield means you pay for the whole wafer but sell only a fraction of it.
Wafer ASP: average selling price of one processed wafer. N2 runs ~$30K; the cost is spread across however many good dies it yields.
High-NA EUV: the next-generation ASML lithography tool, ~EUR 350M each. Intel and Samsung deployed it; TSMC deferred to 2029.
Dual-sourcing: qualifying a second foundry for the same chip so you aren't hostage to one supplier's price or capacity.
Perf-per-watt: performance delivered per unit of power. The metric that decides whether a new node is actually worth its price premium.
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