The real constraint isn't the chip.
Every analyst covering NVIDIA's supply chain reaches the same conclusion within a week: the binding constraint on AI accelerator volume is not logic wafers, not HBM, and not substrate. It is CoWoS, Chip-on-Wafer-on-Substrate, the interposer packaging that fuses the GPU die and its memory stacks into one module. Remove CoWoS and NVIDIA's H-series and B-series GPUs do not exist as products. TSMC has near-monopoly control of CoWoS-L, the exact variant the H100, H200, B100 and B200 all require.
Advanced-packaging revenue at TSMC is tracking to roughly $10-12B in 2026, up from about $3B in 2022, but the tooling expansion cycle runs 12-18 months from order to qualified output. The result: every GPU vendor sourcing CoWoS-L is allocation-constrained through at least Q4 2027. AMD's MI300, Intel's Gaudi 3 and NVIDIA's Blackwell Ultra all compete for the same lines, with NVIDIA commanding first call by virtue of $30B+ in annual TSMC spend.
An NVIDIA compute module on a reference board. The interposer that fuses die and memory is the scarce part. Photo: 4300streetcar / Wikimedia Commons (CC BY 4.0)
TSMC (Taiwan) near-monopoly on CoWoS-L, the packaging the H100, H200, B100 and B200 require.
NVIDIA, AMD, Intel all bid for the same TSMC packaging lines; NVIDIA holds first-allocation rights.
BESI / Lam / ASE supply the bonding, redistribution-layer, and thermal-compression tools.
Ibiden, Shinko, Ajinomoto (Japan) make the ABF substrate, the next bottleneck after CoWoS.
Intel Foundry / Amkor / ASE offer alternative packaging (Foveros, SWIFT, FoCoS) outside TSMC.
1. A GPU die and its HBM memory stacks come off the wafer line as separate pieces.
2. CoWoS mounts both onto a silicon interposer, wiring them together into one compute module.
3. The module is attached to an ABF substrate, the rigid board that connects it to the system.
4. Packaging tool lead times run 12-18 months, so capacity is set long before demand shows up.
5. Finished accelerators ship; whoever holds packaging allocation, not wafers, sets the volume.
Neutral process view. Where a step is single-sourced (TSMC CoWoS-L) is noted without judgment.
Two monopolies, now compounding.
This is structural, not cyclical. As leading-edge logic scaling slows, the gate-pitch improvement from N3 to N2 is roughly 15%, versus 35-40% a generation earlier, performance is increasingly delivered by 3D integration: stacking logic on logic, memory on logic, chiplets on interposers. TSMC built a logic monopoly in the 2010s. It is building a packaging monopoly in the 2020s. The two now reinforce each other, and that compounding, not N2 yields, is what the $1T+ TSMC valuation debate is actually about.
The economics favor packaging more than most realize. TSMC's AP6 facility cost about $2.9B and buys an estimated $6-8B in incremental packaging revenue, a better return than $52-56B of leading-edge capex buying incremental N2. Packaging tools run $50-200M each versus $350M+ for a High-NA EUV scanner. But capital efficiency doesn't shorten the clock: the expansion cycle from committed investment to qualified production is 36 months. The Arizona campus, the first non-Taiwan CoWoS source, qualifies mid-to-late 2026 and reaches volume in 2027. Until then, allocation is the whole game.
The interposer starts as a wafer too. Advanced packaging is increasingly where performance, and margin, is won. Photo: Sangitiana Fararano / Wikimedia Commons (CC BY-SA 2.0)
TSMC, compounding logic and packaging dominance. The packaging-tool makers (BESI, Lam, ASE) with 12-18 month order books. The Japanese ABF substrate trio (Ibiden, Shinko, Ajinomoto) as the next scarce link. And NVIDIA, whose $30B+ spend buys the first-call rights everyone else lacks.
Every GPU vendor without reserved capacity. AMD and Intel, competing for the same lines a tier behind NVIDIA. And any AI-infrastructure buyer whose build plan quietly assumes packaging is elastic when it is the least elastic input in the stack.
The startup opening. The opening is in packaging optionality and intelligence: qualification-as-a-service for CoWoS alternatives, allocation-risk modeling that separates logic from packaging queues, and tooling for the chiplet-integration design problem that every fabless team now faces. The firms that control chiplet integration capability capture the next decade of semiconductor margin.
1. TSMC Investor Day: advanced packaging roadmap (2024/2025) [8 min]
2. DigiTimes: CoWoS capacity ramp estimates (Mar 2026) [5 min]
3. Yole Developpement: advanced packaging TAM (2025) [6 min]
4. Ibiden FY2025 investor reports: ABF substrate lead times [4 min]
CoWoS: Chip-on-Wafer-on-Substrate, TSMC's packaging that mounts a GPU die and its memory onto one silicon interposer. CoWoS-L is the high-end variant AI GPUs need.
Interposer: a silicon layer that sits under the die and memory and wires them together at very high density. The scarce piece in an AI accelerator.
HBM: high-bandwidth memory, the stacked DRAM that sits beside the GPU die and feeds it data fast enough to keep the cores busy.
ABF substrate: the rigid build-up board that connects the packaged module to the rest of the system. A 12-18 month lead-time item, made mostly in Japan.
Allocation: how a constrained supplier rations scarce capacity among customers. With CoWoS, allocation, not money, decides who ships GPUs.
Foveros: Intel's competing 3D packaging technology, offering a non-TSMC geographic option at near-CoWoS interconnect density.
Corrections & coffee: [email protected]
