Memory just got a trillion-dollar multiple.
Memory companies don't get trillion-dollar valuations. Forty years of evidence backs that up: the DRAM industry's hall of fame is a graveyard, Qimonda, Elpida, the memory arms of NEC, Hitachi and Mitsubishi, each killed by the same boom-and-bust cycle. On May 26, 2026, that wisdom broke. Micron touched a $1 trillion valuation, the stock up roughly 19% to around $896 on a UBS upgrade that tripled its target to $1,625. The catalyst wasn't a blowout quarter; it was a structural argument, that long-term HBM contracts with partly fixed pricing have made Micron's earnings less cyclical.
The pricing power is real but widely misunderstood. The $15,000-18,000 figure people cite is the whole GPU, not the memory: a 24GB HBM3E stack is a few hundred dollars to roughly $1,000. The honest comparison is per gigabyte, where HBM runs about 3-5x server DDR5, a genuine premium but not a mythical one, and narrowing toward 1-2x by year-end. The thesis rests on volume and margin, not markup: a 3-5x premium at higher margins, on HBM volumes growing 40-50% a year, reprices anyone with 20%+ share. The question is no longer whether Micron can be worth a trillion. It's whether it can stay there.
A finished wafer. HBM stacks begin as DRAM dies before TSV drilling stacks them. Photo: Sangitiana Fararano / Wikimedia Commons (CC BY-SA 2.0)
Micron (US/Japan) the only US-headquartered DRAM maker; ~20-25% HBM share, fabs in Boise and Hiroshima.
SK Hynix & Samsung (South Korea) the HBM leader (~50%) and the recovering No. 2 (~25-30%).
Applied, Lam, BESI, K&S supply the TSV-drilling and die-bonding tools that actually gate HBM output.
NVIDIA & AMD co-qualify each HBM stack to a specific GPU; a Rubin qual is not an MI400 qual.
US BIS weighing whether advanced HBM exports to China should be restricted.
1. DRAM dies are fabricated, then thinned for stacking.
2. TSV drilling bores vertical channels so 8-12 dies can be stacked and wired together.
3. The finished stack is co-qualified against a named customer GPU, not certified generically.
4. It is integrated via CoWoS packaging right beside the GPU die (see our CoWoS Ceiling brief).
5. The accelerator ships; the HBM vendor's installed TSV tooling, not DRAM wafers, set the ceiling.
Neutral process view. Market-share figures are estimates; no buy/sell view on the equity.
A re-rating, walked through ahead of the revenue.
There were two doors to a trillion dollars: revenue the DRAM cycle has never sustained, or a structural multiple memory has never been granted. The market chose the re-rating and walked through it ahead of the revenue. At roughly $1.1T on $38-40B of FY2026 sales, Micron trades near 25x revenue, a multiple memory has never held, which means the price leans on the less-cyclical, contracted-revenue story rather than on realized fundamentals.
The bull case: US policy has placed Micron inside a regulatory moat no financial model fully prices, the only US-headquartered DRAM maker, $21B of CHIPS-era investment in Idaho and New York, and a footprint diversified away from the East Asian concentration of SK Hynix and Samsung. The bear case is just as concrete: rivals hold more HBM capacity, hyperscalers negotiate brutally, and a multiple this rich is the first thing to compress if HBM4 yields slip. A reversion toward a historical 3-6x sales, even on $45-55B of revenue, implies $200-350B, a 70%+ drawdown. Both cases hinge on the same 18 months of HBM4 qualification.
A decapped chip die. HBM is co-qualified to a specific accelerator, not certified generically. Photo: Ioan Sameli / Wikimedia Commons (CC BY-SA 2.0)
Micron, handed a regulatory moat no rival can buy. SK Hynix, still the volume leader into HBM4. The TSV-tooling and bonding makers (Applied, Lam, BESI, Kulicke & Soffa) with 12-18 month order books. And the US policy goal of domestic, China-excluded strategic memory.
Samsung, whose HBM3E yield stumble handed Micron its share gain and which must prove HBM4. HBM buyers absorbing ~20% price hikes. And anyone holding the equity at 25x revenue if HBM4 qualification disappoints, where the multiple compresses first and fastest.
The startup opening. The opening is in the qualification and concentration gaps: HBM vendor-customer qualification tooling and test services, supply-concentration risk modeling that treats Boise and Hiroshima as single points of failure, and TSV-capacity intelligence for buyers who can't see their vendor's installed tool base. The constraint moved from wafers to tools, and few are mapping it.
1. TrendForce: HBM market share, Q1 2026 [5 min]
2. Micron Q2 FY2026 earnings transcript (Mar 2026) [8 min]
3. US Department of Commerce: CHIPS Act awards (2024) [5 min]
4. UBS upgrade note: Micron $1,625 target (May 2026) [4 min]
HBM: high-bandwidth memory, stacked DRAM that feeds an AI chip data fast enough to keep its cores busy. The product repricing Micron.
HBM4: the next HBM generation, now in qualification, targeted at NVIDIA's Rubin GPUs. The thing the next 18 months turn on.
TSV: through-silicon via, the vertical wiring that connects the stacked dies in an HBM module. Its drilling tools are the real bottleneck.
DRAM: the volatile working memory that HBM is built from. Historically the most brutally cyclical product in semiconductors.
Re-rating: when the market assigns a higher valuation multiple to the same earnings. Micron's $1T rests on one memory has never been granted.
ASP: average selling price. HBM's per-gigabyte ASP runs 3-5x DDR5; the gap, not a mythical markup, is the actual thesis.
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